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HC05V7GRS/D Scheda tecnica(PDF) 52 Page - NXP Semiconductors |
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HC05V7GRS/D Scheda tecnica(HTML) 52 Page - NXP Semiconductors |
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52 / 170 page ![]() SECTION 5: INTERRUPTS Page 38 MC68HC05V7 Specification Rev. 1.0 same interrupt service routine, located at the address specified by the contents of memory locations $3FF4 and $3FF5. 5.9 8-BIT TIMER INTERRUPT This timer can create two types of interrupts. A timer overflow interrupt will occur whenever the 8 bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real time interrupt will occur whenever the programmed time elapses and the enable bit RTIE is set. See SECTION 12 CORE TIMER. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF2 and $3FF3. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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