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HC05V7GRS/D Scheda tecnica(PDF) 74 Page - NXP Semiconductors |
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HC05V7GRS/D Scheda tecnica(HTML) 74 Page - NXP Semiconductors |
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74 / 170 page ![]() SECTION 8: LOW-POWER MODES Page 60 MC68HC05V7 Specification Rev. 1.0 If timer interrupts are enabled, a TIMER interrupt will cause the processor to exit the WAIT Mode and resume normal operation. The Timer may be used to generate a periodic exit from the WAIT Mode. The MCU can be brought out of the WAIT Mode by one of the following: • TIMER interrupt from either timer • IRQ pin external interrupt • Externally or internally generated RESET • Falling edge on any Port A or Port C pin (if enabled) • Rising edge on the MDLC BUS pin Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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