HC05V7GRSSLASHD datasheet(53/170 Pages) NXP

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SECTION 6: RESETS

Page 39

MC68HC05V7 Specification Rev. 1.0

SECTION 6

RESETS

The MCU can be reset from six sources: one external input and five internal restart

conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 6-1. All the

internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure

6-2 for reset timing detail.

Figure 6-1:

Reset Block Diagram

6.1

EXTERNAL RESET (RESET)

The RESET pin is the only external source of a reset. This pin is connected to a Schmitt

trigger input gate to provide an upper and lower threshold voltage separated by a minimum

amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below

the lower threshold and remains in reset until the RESET pin rises above the upper

threshold. This active low input will generate the RST signal and reset the CPU and

peripherals. Termination of the external RESET input or the internal COP Watchdog reset

are the only reset sources that can alter the operating mode of the MCU.

NOTE:

Activation of the RST signal is generally referred to as reset of the device,

unless otherwise specified.

CPU

LATCH

RESET

COP Watchdog

(COPR)

RST

OSC

Data

Address

PH2

To other

peripherals

Low-Voltage

Reset (LVR)

VDD

IRQ/VTST

Mode

Select

To IRQ

logic

LATCH

Power-On Reset

(POR)

VDD

Illegal Address

(ILLADDR)

Address

PH2

CLOCKED

ONE-SHOT

(pulse width = 3 x E-clk)

Disabled STOP

instruction

STOPEN

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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