HC05V7GRSSLASHD datasheet(6/170 Pages) NXP

6 / 170 page

Page vi

MC68HC05V7 Specification Rev. 1.0

11.6

TIMER DURING WAIT MODE ................................................. 73

11.7

TIMER DURING STOP MODE ................................................ 73

SECTION 12

CORE TIMER ................................................................75

12.1

CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08.... 76

12.1.1

CTOF - Core Timer Over Flow............................................ 76

12.1.2

RTIF - Real Time Interrupt Flag .......................................... 76

12.1.3

TOFE - Timer Over Flow Enable ........................................ 76

12.1.4

RTIE - Real Time Interrupt Enable...................................... 76

12.1.5

TOFC - Timer Over Flow Flag Clear ................................... 76

12.1.6

RTFC - Real Time Interrupt Flag Clear ............................... 77

12.1.7

RT1:RT0 - Real Time Interrupt Rate Select ........................ 77

12.2

COMPUTER OPERATING PROPERLY (COP) RESET .......... 77

12.3

CORE TIMER COUNTER REGISTER (CTCR) $09 ................ 78

12.4

TIMER DURING WAIT MODE ................................................. 78

SECTION 13

PULSE WIDTH MODULATOR......................................79

13.1

FUNCTIONAL DESCRIPTION ................................................. 79

13.2

REGISTERS............................................................................. 81

13.2.1

PWM CONTROL................................................................. 81

13.2.2

PWM DATA REGISTERS ................................................... 82

13.3

PWM DURING WAIT MODE.................................................... 82

13.4

PWM DURING STOP MODE ................................................... 82

13.5

PWM DURING RESET ............................................................ 82

SECTION 14

SERIAL PERIPHERAL INTERFACE .............................83

14.1

SPI SIGNAL DESCRIPTION .................................................... 83

14.1.1

Master In Slave Out (MISO/PF3) ........................................ 84

14.1.2

Master Out Slave In (MOSI/PF2) ........................................ 84

14.1.3

Serial Clock (SCK/PF1) ...................................................... 84

14.1.4

Slave Select (SS/PF0) ........................................................ 85

14.2

FUNCTIONAL DESCRIPTION ................................................. 85

14.3

SPI REGISTERS...................................................................... 87

14.3.1

Serial Peripheral Control Register (SPCR) ......................... 87

14.3.2

Serial Peripheral Status Register (SPSR)........................... 88

14.3.3

Serial Peripheral Data I/O Register (SPDR) ....................... 89

14.4

SPI IN STOP MODE ............................................................... 90

14.5

SPI IN WAIT MODE ................................................................. 90

SECTION 15

MESSAGE DATA LINK CONTROLLER.......................91

15.1

OUTLINE .................................................................................. 92

15.1.1

MDLC OPERATING MODES ............................................. 93

15.1.2

MODE DESCRIPTIONS ..................................................... 93

15.2

MDLC CPU INTERFACE ......................................................... 95

15.2.1

OUTLINE ............................................................................ 95

15.2.2

MDLC CONTROL REGISTER (MCR) $0E ......................... 96

15.2.3

MDLC STATUS REGISTER (MSR) $0F............................. 99

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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