HC05V7GRSSLASHD datasheet(50/170 Pages) NXP

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SECTION 5: INTERRUPTS

Page 36

MC68HC05V7 Specification Rev. 1.0

5.5.1.4

IRQF - IRQ Interrupt Request

The IRQF flag bit indicates that an IRQ request is pending. Writing to the IRQF flag bit will

have no effect on it. The IRQF flag bit is cleared when the IRQ vector is fetched prior to the

service routine being entered. The IRQF flag bit can also be cleared by writing a logic one

to the IRQA acknowledge bit to clear the IRQ latch. In this way any additional IRQF flag bit

that is set while in the service routine can be ignored by clearing the IRQF flag bit before

exiting the service routine. If the additional IRQF flag bit is not cleared in the IRQ service

routine and the IRQE enable bit remains set, the CPU will re-enter the IRQ interrupt

sequence continuously until either the IRQF flag bit or the IRQE enable bit is clear. The IRQ

latch is cleared by reset. This flag can be set only when the IRQE enable is set.

5.5.1.5

IRQPCE - Port C IRQ Interrupt Enable

The IRQPCE bit controls whether the IRQPCF flag bit can or cannot initiate an IRQ interrupt

sequence. If the IRQPCE enable bit is set the IRQPCF flag bit can generate an interrupt

sequence. If the IRQPCE enable bit is cleared the IRQPCF flag bit cannot generate an

interrupt sequence. Reset clears the IRQPCE enable bit, thereby disabling Port C IRQ

interrupts. In addition, reset also sets the I-bit, which masks all interrupt sources. Execution

of the STOP or WAIT instructions does not effect the IRQPCE bit.

5.5.1.6

IRQPAE - Port A IRQ Interrupt Enable

The IRQPAE bit controls whether the IRQPAF flag bit can or cannot initiate an IRQ interrupt

sequence. If the IRQPAE enable bit is set the IRQPAF flag bit can generate an interrupt

sequence. If the IRQPAE enable bit is cleared the IRQPAF flag bit cannot generate an

interrupt sequence. Reset clears the IRQPAE enable bit, thereby disabling Port A IRQ

interrupts. In addition, reset also sets the I-bit, which masks all interrupt sources. Execution

of the STOP or WAIT instructions does not effect the IRQPAE bit.

NOTE:

The IRQPAE and IRQPCE mask bits must be set prior to entering STOP

or WAIT modes if Port IRQ interrupts are to be enabled.

5.5.1.7

IRQE - IRQ Interrupt Enable

The IRQE bit controls whether the IRQF flag bit can or cannot initiate an IRQ interrupt

sequence. If the IRQE enable bit is set the IRQF flag bit can generate an interrupt

sequence. If the IRQE enable bit is cleared the IRQF flag bit cannot bet set and therefor

cannot generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling

IRQ interrupts once the I-bit is cleared. Execution of the STOP or WAIT instructions causes

the IRQE bit to be set in order to allow the external IRQ to exit these modes. In addition,

reset also sets the I-bit, which masks all interrupt sources.

5.5.2

External Interrupt Timing

If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and

external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched

immediately following the falling edge of the IRQ source. It is then synchronized internally

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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