HC05V7GRSSLASHD datasheet(93/170 Pages) NXP

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SECTION 13: PULSE WIDTH MODULATOR

Page 79

MC68HC05V7 Specification Rev. 1.0

SECTION 13

PULSE WIDTH MODULATOR

The pulse width modulator (PWM) system has one 6-bit channel (PWMA). Preceding the

6-bit (

÷64) PWM are two programmable prescalers.The PWM frequency is selected by

choosing the desired divide option from the programmable prescalers. Note that the PWM

clock input is fosc, which is twice the bus frequency. The PWM frequency will be fosc/

(PSA+PSB+64) where PSA and PSB are the values selected by the A and B prescaler and

64 comes from the 6-bit modulus counter. See Table 13-1 for precise values. E is the

internal bus frequency fixed to half of the external oscillator frequency.

Figure 13-1:

PWM Block Diagram

13.1

FUNCTIONAL DESCRIPTION

The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM

Data Register yields an “low” output (0%), but a $3F yields a duty of 63/64. To achieve the

100% duty (“high” output), the polarity control bit is set to zero while the data register has

$00 in it.

When not in use, the PWM system can be shut off to save power by clearing the clock rate

select bits PSA0 and PSA1 in PWMCR.

Writes to the PWM data register are buffered and can therefore be performed at any time

without affecting the output signal. When the PWM subsystem is enabled, a write to the

PWM Control Register will become effective immediately.

6-BIT COUNTER

(

÷64)

PWM DATA

MODULUS &

COMPARATOR

PWM

PIN LOGIC

PWMA

÷1, ÷8, ÷16

fosc

PWM CONTROL REGISTER and BUFFER

PWM DATA

BUFFER

SCLK

÷1-16

RCLK

Integer divide

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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