HC05V7GRSSLASHD datasheet(100/170 Pages) NXP

100 / 170 page

SECTION 14: SERIAL PERIPHERAL INTERFACE

Page 86

MC68HC05V7 Specification Rev. 1.0

Figure 14-2:

Serial Peripheral Interface Block Diagram

In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL

bit in the SPCR, until data is written to the shift register, at which point eight clocks are

generated to shift the eight bits of data and then SCK goes idle again.

In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock

at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is

received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift

is written into the shift register, then the slave waits for a clock train from the master to shift

the data out on the slave’s MISO line.

Figure 14-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.

DIVIDER

÷2 ÷4 ÷16 ÷32

SELECT

8-BIT SHIFT REG

READ DATA BUFF

MSB

LSB

CLOCK

LOGIC

SPI CLOCK (MASTER)

MSTR

SPE

SPI CONTROL REGISTER

INTERNAL

DATA BUS

SPI INTERRUPT

REQUEST

SPI STATUS REGISTER

SPI CONTROL

INTERNAL

MCU CLOCK

PF1/

PF0/

PF2/

PF3/

MISO

MOSI

SCK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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