HC05V7GRSSLASHD datasheet(130/170 Pages) NXP

130 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 116

MC68HC05V7 Specification Rev. 1.0

15.5.3

J1850 VPW SYMBOLS

Variable Pulse Width Modulation (VPW) is an encoding technique in which each bit is

defined by the time between successive transitions, and by the level of the bus between

transitions, active or passive. Active and passive bits are used alternately.

Each logic one or logic zero contains a single transition, and can be at either the active or

passive level and one of two lengths, either 64

µs or 128 µs (T

NOM at 10.4 kbps baud rate),

depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS symbols

will always be encoded at an assigned level and length. See Figure 15-11:

J1850 VPW

Symbols

Each message will begin with an SOF symbol, an active symbol, and therefore each data

byte (including the CRC byte) will begin with a passive bit, regardless of whether it is a logic

one or a logic zero.

All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit

rate.

128

µs

Active

Passive

µs

Logic "0"

128

µs

Active

Passive

µs

Logic "1"

200

µs

Active

Passive

Start of Frame

200

µs

End of Data

280

µs

Active

Passive

End of Frame

≥ 280 µs

Break

(a)

(b)

(c)

(d)

(e)

(f)

Figure 15-11 :

J1850 VPW Symbols

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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