HC05V7GRSSLASHD datasheet(162/170 Pages) NXP

162 / 170 page

SECTION 17: ELECTRICAL SPECIFICATIONS

Page 148

MC68HC05V7 Specification Rev. 1.0

SERIAL PERIPHERAL INTERFACE (SPI) TIMING

(VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH)

* Signal production depends on software.

** Assumes 200 pF load on all SPI pins.

Num

Characteristic

Symbol

Min

Max

Unit

Operating Frequency

Master

Slave

(M)

(S)

0.5

4.2

MHz

Cycle Time

Master

Slave

CYC

(M)

CYC

(S)

2.0

240

—

CYC

Enable Lead Time

Master

Slave

LEAD

(M)

tlead(s)

240

—

Enable Lag Time

Master

Slave

LAG

(M)

LAG

(S)

240

—

Clock (SCK) High Time

Master

Slave

(SCKH)M

(SCKH)S

340

190

—

Clock (SCK) Low Time

Master

Slave

(SCKL)M

(SCKL)S

340

190

—

Data Setup Time (Inputs)

Master

Slave

(M)

(S)

100

—

Data Hold Time (Inputs)

Master

Slave

(M)

(S)

100

—

Access Time (Time to Data Active from High-

Impedance State)

Slave

120

Disable Time (Hold Time to High-Impedance State)

Slave

DIS

—

240

Data Valid (After Enable Edge)**

(S)

—

240

Data Hold Time (Output) (After Enable Edge)

0—

Rise Time (20% VDD to 70% VDD, CL =200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

—

100

2.0

Fall Time (70% VDD to 20% VDD, CL =200 pF)

SPI Outputs (SCK, MOSI, and MISO)

SPI Inputs (SCK, MOSI, MISO, and SS)

—

100

2.0

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 162 Page - NXP Semiconductors

HC05V7GRS/D Scheda tecnica(HTML) 162 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL