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HC05V7GRS/D Scheda tecnica(PDF) 102 Page - NXP Semiconductors |
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HC05V7GRS/D Scheda tecnica(HTML) 102 Page - NXP Semiconductors |
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102 / 170 page ![]() SECTION 14: SERIAL PERIPHERAL INTERFACE Page 88 MC68HC05V7 Specification Rev. 1.0 CPOL - Clock Polarity When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. Figure 14-1: Data Clock Timing Diagram. CPHA - Clock Phase The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA=0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin may be thought of as a simple output enable control. Figure 14-1: Data Clock Timing Diagram. SPR1 and SPR0 - SPI Clock Rate Selects These two bits select one of four baud rates (Figure 14-5) to be used as SCK if the device is a master; however, they have no effect in the slave mode. Figure 14-5: Serial Peripheral Rate Selection 14.3.2 Serial Peripheral Status Register (SPSR) Figure 14-6: SPI Status Register (SPSR) SPIF - SPI Transfer Complete Flag The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an access of the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. SPR1 SPR0 0 0 0 1 1 0 1 1 INT MCU CLOCK DIVIDED BY 2 4 16 32 SPIF — MODF ———— WCOL $0B 0 000000 0 RESET: Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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