HC05V7GRSSLASHD datasheet(110/170 Pages) NXP

110 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 96

MC68HC05V7 Specification Rev. 1.0

15.2.2

MDLC CONTROL REGISTER (MCR) $0E

This register is used to configure and control the MDLC.

All bits may be read in all modes of MCU operation.

Bits 0, 4 and 5 may be written to only once after reset after which they become read only

bits.

Bit 1 may always be written.

Bits 6 and 7 may only be set by the CPU, clears are ignored. These bits are cleared

automatically by the MDLC when the appropriate action is completed.

15.2.2.1

RXBM - Receive Block Mode

This bit is set to indicate to the MDLC that the next incoming message will be a block

message. (See 15.7.4 RECEIVING A MESSAGE IN BLOCK MODE).

If this bit is set and the Rx Buffer being loaded with data bytes received from the multiplex

bus is filled or the last byte of the current block message has been received, a CPU

interrupt request is generated (if the IE bit is set) and the Rx Message Successful (RXMS)

bit will be set, just as in normal message reception. Additional incoming bytes will be placed

into the next available Rx Buffer.

The RC3-0 bits of the MRSR register only reflect the byte count of the Rx Buffer available

to the CPU and not a cumulative value of the number of bytes in the block message.

Once set, this bit can only be cleared automatically by the MDLC. It will be cleared following

the successful reception of a message or immediately upon the receiver detecting an error

(CRC, invalid bit etc.), reverting the MDLC to its usual mode of operation in which normal

message lengths are expected. This bit will also be cleared if both Rx Buffers fill, they are

not serviced and further data bytes are received (Block mode ’overflow’ occurs).

The receiver will compute a cumulative CRC throughout the reception of a block message,

and will not treat the CRC calculation as complete until an End of Data (EOD) symbol is

received. At this time the MDLC will automatically clear the RXBM bit indicating to the

programmer that the block message has ended.

15.2.2.2

TXAB - Transmit Abort

This bit is set by the programmer to abort an in-progress transmission. The subsequent

actions depend upon what the transmitter is doing at the point in time when the CPU

interface recognizes this command.

Figure 15-3:

MDLC Control Register (MCR)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

WCM

RESET

00100000

TXAB

RXBM

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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