HC05V7GRSSLASHD datasheet(112/170 Pages) NXP

112 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 98

MC68HC05V7 Specification Rev. 1.0

15.2.2.3

R1, R0 - Rate Select

These bits determine the operating frequency of the MDLC.

The nominal frequency (fmdlc) of the MUX Interface clock must always be 1.048576 MHz

in order for J1850 bus communication to take place. Therefore, the value programmed into

these bits is dependant upon the chosen MCU system clock frequency per the following

table.

In the case of R1=R0=0, the oscillator clock is used instead of E clock.

The case of R1=R0=1 must not be selected for the MC68HC05V7 and MC68HC705V8.

15.2.2.4

IE - Interrupt Enable

This bit determines whether the MDLC will generate CPU interrupt requests in the Run

mode. Clearing the IE bit will not prevent CPU interrupt requests when exiting the MDLC

Stop or MDLC Wait modes.

When set, the MDLC will generate CPU interrupt requests. Interrupt requests will be

maintained until all of the interrupt request sources are cleared, by performing the specified

actions upon the MDLC registers.

When clear, the MDLC will not generate CPU interrupt requests. Interrupts that were

pending at the time that this bit is cleared may be lost.

15.2.2.5

WCM - Wait Clock Mode

This bit determines the operation of the MDLC during CPU Wait mode. See 15.7.6 MDLC

WAIT MODE for more details on its use.

When set, the MDLC internal operating clocks will be stopped during CPU Wait mode.

When clear, the MDLC internal operating clocks will stay running during CPU Wait mode.

Table 15-2:

MDLC Rate Selection

Clock Frequency

Division

MDLC

OSC =1.048576 MHz

P=524Khz)

1.048576 MHz

P=1.048576 MHz

1.048576 MHz

P=2.097152 MHz

1.048576 MHz

P=4.194304 MHz

1.048576 MHz

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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