HC05V7GRSSLASHD datasheet(143/170 Pages) NXP

143 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 129

MC68HC05V7 Specification Rev. 1.0

received bytes as part of an in-progress message until the MDLC clears the RXBM bit.

Once the received data bytes of interest to the CPU have been analyzed, the MCU must

write any quantity to the MRSR register to free it for the next received message.

15.7.4

RECEIVING A MESSAGE IN BLOCK MODE

Although not a part of the SAE J1850 protocol, the MDLC does allow for a special ’Block

mode’ of operation for the receiver only. The MDLC cannot transmit Block mode messages.

As far as the MDLC is concerned, a Block mode message is simply a long J1850 frame that

contains an indefinite number of data bytes. All of the other features of the frame remain

the same, including the SOF, CRC and EOD symbols.

Another node wishing to send a Block mode transmission must first inform all other nodes

on the network that this is about to happen. This is usually accomplished by sending a

special predefined message. MDLC nodes wishing to receive the message should set the

Receive Block Mode (RXBM) bits in the MDLC Control Register (MCR).

Since the MDLC only has a finite amount of received data buffering available, the

programmer must ensure that received data is moved from the Rx Buffers to the application

memory throughout the duration of the Block mode message. The MDLC aids the user by

utilizing both Rx Buffers to buffer the arriving data bytes in Block mode. As soon as one Rx

Buffer fills, the incoming data ’spills over’ into the second Rx Buffer, the Received Message

Successfully (RXMS) bit in the MDLC Status Register (MSR) will be set and a CPU interrupt

request is generated, signalling to the user that an Rx Buffer must be emptied and "given

back" in the same manner as explained for receiving normal messages. This alternate

filling of Rx Buffers gives plenty of time for one Rx Buffer to be emptied by the user, while

the other one is being filled by the MDLC.

The Rx Buffers will continue to be alternately filled and emptied until an EOD symbol, or

error, is detected. Throughout the reception of the Block mode message, the MDLC will

calculate a running CRC. When an EOD symbol is finally detected, the CRC will be

checked and, if correct, the Received Message Successfully (RXMS) bit in the MDLC

Status Register (MSR) will be set, the RXBM bit will be cleared and a CPU interrupt request

will be generated.

Should the second Rx Buffer ever fill, then it will attempt to spill over into the first Rx Buffer

which (hopefully) has been emptied in time. If not, an overflow condition is detected, both

Rx Buffer pointers are reset (discarding the data currently held in the Rx Buffers), the

RXBM bit will be cleared, and the MDLC will silently wait for the next normal J1850

message to be received. Any other errors detected during the reception of a Block mode

message (for example, invalid symbols) will result in these same actions.

MDLC nodes not wishing to receive a Block mode message can leave the RXBM bit clear,

causing all Block mode messages to be completely ignored. The next normal J1850

message to appear on the bus will be automatically received as long as it contains no

errors.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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