HC05V7GRSSLASHD datasheet(141/170 Pages) NXP

141 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 127

MC68HC05V7 Specification Rev. 1.0

15.6.3

PINS

There are seven pins associated with the MDLC module. Figure 15-16:

MDLC Physical

Interface Outline gives an example mechanization. A brief description of each pin follows.

15.6.3.1

REXT1, REXT2

These are external biasing resistor tie points for transmitter waveshaping and they must be

referenced to the VDD pin through lines which are as low impedance and low noise as

possible to ensure consistent operation.

15.6.3.2

BUS

This is the half-duplex data line for J1850 communications.

15.6.3.3

LOAD

This is the switched ground connection for the J1850 bus, via an RC load.

15.6.3.4

VBATT

This is the source for battery voltage for the MDLC. This power supply pin must be

protected against transient and fault conditions.

To protect against loss of battery, a low voltage protect circuit within the transceiver

disables drive from the BUS pin to prevent erroneous messages from being transmitted.

Nominal trip points are VTIVB Volts on VBATT and VRIVD Volts on VCCA.

15.6.3.5

VCCA

This is the MDLC analog transceiver power supply input and is nominally 5V. This supply

must be kept as low impedance and low noise as possible. It may be supplied from a

different voltage regulator source than VDD.

Whenever the voltage on this pin rises from zero to its nominal operating value, the

Physical Interface detects this power-on condition and resets its control circuits. Also,

whenever the voltage on this pin falls below its minimum operating value, the MDLC analog

circuitry will return to its reset state.

15.6.3.6

VSSA2

This is the Physical Interface power supply ground. This supply must be kept as low

impedance and low noise as possible. It must be connected directly to the same grounding

point that the main MCU Vss uses.

15.6.3.7

Decoupling

Good supply decoupling, as close as possible to the supply pins, is absolutely essential to

guarantee correct operation, minimize RFI and maximize analog performance. MDLC and

non-MDLC supply lines should be kept separate to minimize interaction. Emphasis should

be placed on keeping supply and ground line impedances as low as possible, with

preference given to ground lines if some compromise is necessitated. Ground planes and

wide, short, PCB traces can help significantly here. Decoupling capacitors should be of low

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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