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HC05V7GRS/D Scheda tecnica(PDF) 154 Page - NXP Semiconductors |
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HC05V7GRS/D Scheda tecnica(HTML) 154 Page - NXP Semiconductors |
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154 / 170 page  SECTION 17: ELECTRICAL SPECIFICATIONS Page 140 MC68HC05V7 Specification Rev. 1.0 17.3 DC ELECTRICAL CHARACTERISTICS (VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = -40°C to +85°C, unless otherwise noted) (I Load = -0.8 mA) PA0-7, PB0-7, PC0-7, PF0-3, PWM Output voltage I Load = 10.0 µA Unit Max Typ Min Symbol Characteristic V 0.1 — — V OL — — V DD -0.1 V OH Output High Voltage — — V DD -0.8 V OH V Output Low Voltage (I Load = 1.6 mA) PA0-7, PB0-7, PC0-7, PF0-3,PWM Input High Voltage V DD V BATT — V IH Ports A, B, C VIGN V Input Low Voltage — V IL Ports A, B, C VIGN V V SS V SS 0.4 — --- V OL V --- --- --- --- I DD I DD VDD Supply Current (see Notes) mA Run mA Wait SPI, TIMER, A/D, PWM, COP, and LVR enabled Stop (Regulator disabled, LVR enabled) 25 °C 0 °C to +70°C (Standard) -40 °C to +85°C (Extended) I DD I DD I DD --- TBD TBD 200 3 5 --- --- --- TBD TBD µA µA µA I/O Ports Hi-Z Leakage Current ±1 — I IL PA0-7, PB0-7, PC0-7, PF0-3 µA — Input Current ±1 — I IN RESET, IRQ, OSC1, TCAP, PD0-7,PE0-7, SS µA — Capacitance * 12 — C OUT Ports (as Input or Output) pF — RESET, IRQ, OSC1, OSC2, TCAP, PD0-7,PE0-7, SS C IN —8 —pF Low Voltage Reset Inhibit 4.2 — V LVRI V 3.5 Low Voltage Reset Recover 4.5 — V LVRR V 3.6 Low Voltage Reset Inhibit/Recover Hysteresis 0.3 0.2 H LVR V 0.1 --- I BATT VBATT Supply Current at 12V 25 TBD µA --- I BATT 800 TBD µA --- I BATT 250 TBD µA Stop Regulator disabled Stop Regulator enabled (includes STOP IDD , LVR disabled) Run Regulator disabled (Transceiver current) --- mA Wait above modules off I DD 1.2 --- 25 °C (LVR disabled) I DD --- 100 --- µA Input High Voltage V DD V IH Ports D, E, F, IRQ, RESET, OSC1 V 0. 7×V DD — Input Low Voltage 0. 3×V DD 0. 3×V BATT — V IL Ports D, E, F, IRQ, RESET, OSC1 V V SS V SS 0. 8×V DD 0. 8×V BATT 0. 4×V DD 0. 4×V BATT Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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