HC05V7GRSSLASHD datasheet(118/170 Pages) NXP

118 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 104

MC68HC05V7 Specification Rev. 1.0

The MDLC has three 11 byte buffer arrays. The transmit circuitry uses a single Tx Buffer,

that for certain periods of time may have either the CPU or the MDLC access "locked out".

The receiver has two Rx Buffers but only one can appear in the MCU memory map at a

time. The CPU will have access to whichever Rx Buffer was filled the earliest. While the

CPU is reading data from one Rx Buffer, the MDLC may place incoming data into the other

Rx Buffer. When the CPU writes to the MRSR register, the Rx Buffer which the CPU had

access to is "given back" to the MDLC making it available for another incoming message.

The MDLC Tx Buffer is writable by the CPU at all times but it is not readable. A read of the

Tx buffer will result in an unknown value. The Rx Buffers can be read by the CPU at

anytime. However, writes to the Rx Buffer will not have an effect on the buffer’s content.

NOTE:

The contents of the Tx Buffer are not guaranteed to remain intact following

a transmission so the Tx Buffer should be completely reloaded for each

new message to be sent.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 118 Page - NXP Semiconductors