HC05V7GRSSLASHD datasheet(121/170 Pages) NXP

121 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 107

MC68HC05V7 Specification Rev. 1.0

As long as the CPU has possession of the Tx Buffer, the MDLC cannot transmit. Once the

CPU has finished with the contents of the Tx Buffer, it may be "given back" to the MDLC by

writing the message body length ’n’ to the MDLC Tx Control Register (MTCR).

Starting from the first entry of the Tx Buffer, the MDLC fetches each data byte from a filled

entry of the Tx Buffer, the Tx Buffer pointer is incremented and the MDLC attempts to

transmit the data byte onto the J1850 bus. This continues until the last byte of the message

body has been fetched, arbitration is lost or an error occurs. If the transmitted message is

sent error-free then a CRC is appended, the filled Tx Buffer is given back to the CPU, the

Transmitted Message Successfully (TXMS) bit in the MDLC Status Register (MSR) is set,

and a CPU interrupt request is made (if interrupts are enabled). This sequence is then

repeated as long as normal data transmission takes place.

If any type of transmission error is detected by the MDLC as a message is being transmitted

onto the J1850 bus, the internal Tx Buffer pointer will be reset to zero, effectively flushing

the data to be sent, and the MDLC will automatically abort transmission. When this occurs

the MDLC will not generate a CPU interrupt request and will silently wait for the next write

to the MTCR register.

If a loss of arbitration occurs while the MDLC is attempting to transmit a message, the

MDLC will immediately halt transmission and become a receiver. As soon as an idle bus

condition is detected, the MDLC will again attempt to transmit the message onto the

multiplex bus. This automatic retry will continue until the message is transmitted

successfully, an error is detected during transmission, or the TXAB bit is set by the CPU.

Since the Tx Buffer is 11 bytes long, any value greater than or equal to $0C written to the

MTCR register will create a Tx Buffer overflow error and cause the MDLC to not transmit

that message. Attempts to send a zero byte message body length (value of $00 written to

MTCR) will also cause the MDLC to not transmit that message.

At the end of a transmission, successful, unsuccessful or aborted, the MTCR register is

automatically cleared. If interrupts are enabled, the programmer should not poll the MTCR

Instead, since the MDLC receives every message that it sends, the programmer should

check that each message that is attempted to be sent is received back within some

acceptable amount of time before attempting to send another message. Failure to receive

back a message that has been sent in a timely fashion might indicate that some network

fault exists.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 121 Page - NXP Semiconductors