HC05V7GRSSLASHD datasheet(119/170 Pages) NXP

119 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 105

MC68HC05V7 Specification Rev. 1.0

15.3.2

RX BUFFERS

The Rx Buffers consist of two 11-byte arrays, with 8 bits per byte. Only one message may

occupy each Rx Buffer array at any time. Each Rx Buffer array has an internal register (the

’Rx Buffer pointer’) associated with it in which the length of the message body is recorded.

Following a reset, the MDLC has "possession" of the two empty Rx Buffers and their

associated Rx Buffer pointers are both reset to zero. Neither Rx Buffer appears in the CPU

memory map at this time, attempts to read them will return undefined data.

As each data byte of an incoming message is received by the MDLC, it is placed into the

next available entry of one of the Rx Buffers and the Rx Buffer pointer is incremented. This

continues until the end of the message is detected or an error occurs.

Figure 15-7:

MDLC Rx/Tx Buffers Outline

Rx Buffer

Array

Rx Buffer

Array

11 bytes

MRSR

MTCR

MUX

MDLC

Rx Logic

MDLC

Tx Logic

CPU

From

CPU

MDLC automatically

toggles multiplexer (MUX)

when one buffer is full.

Write to MRSR

"gives back" buffer

Indicates active path

Tx Buffer

Array

to MDLC for Rx.

Write to MTCR

"gives back" buffer

to MDLC for Tx.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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