HC05V7GRSSLASHD datasheet(137/170 Pages) NXP

137 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 123

MC68HC05V7 Specification Rev. 1.0

15.6

MDLC PHYSICAL INTERFACE

All analog functions involved in transmitting and receiving from the J1850 bus are

performed by the Physical Interface. The Physical Interface serves to buffer the incoming

messages, wave-shape the messages being transmitted, and protect the MDLC from

transients occurring on the J1850 bus.

15.6.1

OUTLINE

The receiver analog comparator and transmitter drivers are included in the MDLC Physical

Interface and together are referred to as the "transceiver".

The transceiver provides a waveshaped 7V bus waveform in response to a timed logic

signal from the MUX Interface. The transceiver actively drives the bus high, and passively

lets an RC network pull the bus low. In order to achieve the 7V level necessary for the bus

signal, the transceiver uses a battery supply (VBATT) which is nominally 12V. The

transceiver also receives bus waveforms and provides the MUX Interface with unfiltered

input data

A low power mode of operation is automatically entered if the CPU executes a STOP or

WAIT instruction.

In the event that ground is lost, the transceiver senses this condition and releases the bus

by switching the LOAD pin to a high impedance instead of a low impedance to ground.The

transceiver also protects the MDLC by not passing on any standard disruptive or non-

disruptive signals seen on the bus to the rest of the MDLC.

The Physical Interface contains its own power-on reset circuit that is used to reset its

control circuitry whenever a power-on condition is detected.

Physical Interface

To CPU

Protocol Handler

MUX Interface

CPU Interface

Rx/Tx

Buffers

To J1850 Bus

MDLC

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 137 Page - NXP Semiconductors