HC05V7GRSSLASHD datasheet(123/170 Pages) NXP

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SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 109

MC68HC05V7 Specification Rev. 1.0

15.4.3

STATE MACHINE

All of the functions associated with performing the protocol are executed or controlled by

the State Machine. The State Machine is responsible for framing, collision detection,

arbitration, CRC generation/checking, and error detection. The following sections describe

the MDLC’s actions in a variety of situations.

15.4.3.1

In-Frame Response

The MDLC does not support the In-Frame Response (IFR) feature of J1850. If the MDLC

receives an IFR, it will ignore the response (not placing it in an Rx Buffer) and wait for the

End of Frame (EOF) symbol.

15.4.3.2

4x Speed Mode

The MDLC can exist on the same J1850 bus as modules which use a special 4x mode of

J1850 VPW operation. The MDLC treats 4x mode messages as noise and ignores them.

The MDLC will wait for a valid SOF or BREAK at 10.4 kbps to resume normal operation.

15.4.3.3

Block Mode

While the MDLC can only transmit a maximum of 12 bytes (including CRC byte) in a given

message, it has the ability to receive a message of unlimited length. Like 4x mode, the

programmer will have to determine from a received message that Block mode is to be

enabled. The programmer then sets the “Receive Block Message” (RXBM) bit in the MDLC

Control Register (MCR) to indicate to the MDLC that the following message will be longer

than 12 bytes and not to treat it as a message over length error.

15.4.3.4

Arbitration

Arbitration is performed by the MDLC simply by comparing the data being received from

the J1850 bus with the data being transmitted. This is done by latching the data being

transmitted into a comparator, where it is compared with the data being received from the

J1850 bus. If a valid data bit is received which has a higher priority over what was

transmitted (0 over 1), arbitration is then lost, and the transmitter stops transmitting until a

valid EOF symbol is received from the J1850 bus. See 15.5.5 MESSAGE ARBITRATION

for more information.

If an invalid bit or a symbol in a non-byte boundary is detected, the transmitter will also stop

transmitting.

In VPW, an active signal will always dominate a passive one, and a shorter passive symbol

will dominate a longer passive symbol. This ensures that a logic zero will dominate a logic

one, and the message with the highest priority (lowest value) will win arbitration. See 15.5.5

MESSAGE ARBITRATION for more details.

15.4.3.5

J1850 Bus Errors

The MDLC detects several types of transmit and receive errors which can occur during the

transmission of a message onto the J1850 bus.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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